Multibit Continuous Time Σ∆ Modulators with a Reduced Number of Comparators

A drawback of continuous time Σ∆-modulators is their sensitivity to clock jitter. An appropriate way to counteract this is to use a multi bit feedback loop. This requires a high resolution multi bit quantizer. However, every extra bit in the quantizer doubles its complexity and power consumption. In this paper, a new Σ∆-modulator architecture is proposed. The implementation issues are discussed and the modulators’ performance was compared with a conventional modulator through computer simulations. In the simulation examples the modulator had a quantizer with a quantization step corresponding to 6bit accuracy. Compared to the conventional modulator, the proposed architectures achieves the same performance while the required number of comparators in the high resolution quantizer can be reduced significantly.